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DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 8 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
ANSS
2001
IEEE
15 years 8 months ago
Epoch Load Sharing in a Network of Workstations
This paper examines load sharing in a network of workstations (NOW). It proposes a special load sharing method referred to as epoch load sharing. With this policy, load is evenly ...
Helen D. Karatza, Ralph C. Hilzer Jr.
ISCA
1997
IEEE
98views Hardware» more  ISCA 1997»
15 years 7 months ago
Target Prediction for Indirect Jumps
As the issue rate and pipeline depth of high performance superscalar processors increase, the amount of speculative work issued also increases. Because speculative work must be th...
Po-Yung Chang, Eric Hao, Yale N. Patt
VLDB
1995
ACM
149views Database» more  VLDB 1995»
15 years 7 months ago
Managing Intra-operator Parallelism in Parallel Database Systems
Abstract: Intra-operator(or partitioned) parallelism is a well-established mechanism for achieving high performance in parallel database systems. However, the problem of how to exp...
Manish Mehta 0002, David J. DeWitt
LREC
2010
155views Education» more  LREC 2010»
15 years 5 months ago
A Named Entity Labeler for German: Exploiting Wikipedia and Distributional Clusters
Named Entity Recognition is a relatively well-understood NLP task, with many publicly available training resources and software for English. Other languages tend to be underserved...
Grzegorz Chrupala, Dietrich Klakow