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IEEEPACT
2005
IEEE
15 years 3 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
DAC
2005
ACM
14 years 11 months ago
Partitioning-based approach to fast on-chip decap budgeting and minimization
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, ...
ICS
2005
Tsinghua U.
15 years 3 months ago
High performance support of parallel virtual file system (PVFS2) over Quadrics
Parallel I/O needs to keep pace with the demand of high performance computing applications on systems with ever-increasing speed. Exploiting high-end interconnect technologies to ...
Weikuan Yu, Shuang Liang, Dhabaleswar K. Panda
101
Voted
VIS
2004
IEEE
164views Visualization» more  VIS 2004»
15 years 10 months ago
Real-Time Motion Estimation and Visualization on Graphics Cards
We present a tool for real-time visualization of motion features in 2D image sequences. The motion is estimated through an eigenvector analysis of the spatiotemporal structure ten...
Christoph S. Garbe, Robert Strzodka
ASPDAC
2008
ACM
101views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Interconnect modeling for improved system-level design optimization
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Ale...