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IWNAS
2006
IEEE
16 years 1 days ago
A Fast Read/Write Process to Reduce RDMA Communication Latency
RDMA reduces network latency by eliminating unnecessary copies from network interface cards to application buffers, but how to reduce memory registration cost is a challenge. Prev...
Li Ou, Jizhong Han
HOTOS
2009
IEEE
15 years 10 months ago
Reinventing Scheduling for Multicore Systems
High performance on multicore processors requires that schedulers be reinvented. Traditional schedulers focus on keeping execution units busy by assigning each core a thread to ru...
Silas Boyd-Wickizer, Robert Morris, M. Frans Kaash...
ISCA
1991
IEEE
121views Hardware» more  ISCA 1991»
15 years 9 months ago
IXM2: A Parallel Associative Processor
This paper describes a parallel associative processor, IXM2, developed mainly for semantic network processing. IXM2 consists of 64 associative processors and 9 network processors,...
Tetsuya Higuchi, Tatsumi Furuya, Ken'ichi Handa, N...
EXPERT
2007
109views more  EXPERT 2007»
15 years 6 months ago
Mexar2: AI Solves Mission Planner Problems
s planners work at a higher abstraction level while it performs low-level, often-repetitive tasks. It also helps them produce a plan rapidly, explore alternative solutions, and cho...
Amedeo Cesta, Gabriella Cortellessa, Michel Denis,...
ICDCS
2010
IEEE
15 years 10 months ago
Sifting through Network Data to Cull Activity Patterns with HEAPs
—Today’s large campus and enterprise networks are characterized by their complexity, i.e. containing thousands of hosts, and diversity, i.e. with various applications and usage...
Esam Sharafuddin, Yu Jin, Nan Jiang, Zhi-Li Zhang