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ASPLOS
1998
ACM
15 years 8 months ago
Compiler-Controlled Memory
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
Keith D. Cooper, Timothy J. Harvey
ISCA
1996
IEEE
120views Hardware» more  ISCA 1996»
15 years 8 months ago
Missing the Memory Wall: The Case for Processor/Memory Integration
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
Ashley Saulsbury, Fong Pong, Andreas Nowatzyk
ESANN
2006
15 years 5 months ago
Construction of a memory management system in an on-line learning mechanism
This paper is the first of a two paper series that deals with an important problem in on-line learning mechanisms for autonomous agents that must perform non trivial tasks and oper...
Francisco Bellas, José Antonio Becerra, Ric...
CCS
2010
ACM
15 years 4 months ago
Dismantling SecureMemory, CryptoMemory and CryptoRF
The Atmel chip families SecureMemory, CryptoMemory, and CryptoRF use a proprietary stream cipher to guarantee authenticity, confidentiality, and integrity. This paper describes th...
Flavio D. Garcia, Peter van Rossum, Roel Verdult, ...
ARCS
2006
Springer
15 years 8 months ago
Adding Low-Cost Hardware Barrier Support to Small Commodity Clusters
The performance of the barrier operation can be crucial for many parallel codes. Especially distributed shared memory systems have to synchronize frequently to ensure the proper o...
Torsten Hoefler, Torsten Mehlan, Frank Mietke, Wol...