38 search results - page 4 / 8 » Activity Packing in FPGAs for Leakage Power Reduction |
108
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DSD
2008
IEEE
14 years 11 months ago
2008
IEEE
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache, traditionally used for reducing...
108
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JCSC
2002
14 years 9 months ago
2002
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
75
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ICCD
2002
IEEE
15 years 6 months ago
2002
IEEE
Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for...