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» Activity Packing in FPGAs for Leakage Power Reduction
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GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
CASES
2006
ACM
15 years 3 months ago
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
Mark Hempstead, Gu-Yeon Wei, David Brooks
DAC
2005
ACM
14 years 11 months ago
Keeping hot chips cool
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
ISCAS
2007
IEEE
110views Hardware» more  ISCAS 2007»
15 years 4 months ago
A Novel Active Decoupling Capacitor Design in 90nm CMOS
—On-chip decoupling capacitors (decaps) are generally used to reduce power supply noise. Passive decap designs are reaching their limits in 90nm CMOS technology due to higher ope...
Xiongfei Meng, Karim Arabi, Resve Saleh
ISLPED
2003
ACM
113views Hardware» more  ISLPED 2003»
15 years 2 months ago
Reducing power density through activity migration
Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Exc...
Seongmoo Heo, Kenneth C. Barr, Krste Asanovic