433 search results - page 11 / 87 » Activity-driven clock design for low power circuits |
ISCAS
2007
IEEE
15 years 6 months ago
2007
IEEE
—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when b...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
Resonant clocking holds the promise of trading speed for energy in CMOS circuits that can afford to operate at low frequency, like hearing aids. An experimental chip with 110k tra...
TVLSI
2010
14 years 6 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
ASPDAC
2004
ACM
15 years 5 months ago
2004
ACM
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...
ISLPED
2000
ACM
15 years 4 months ago
2000
ACM
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented cir...