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» Activity-driven clock design for low power circuits
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ISQED
2005
IEEE
169views Hardware» more  ISQED 2005»
15 years 5 months ago
ASLIC: A Low Power CMOS Analog Circuit Design Automation
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
Jihyun Lee, Yong-Bin Kim
GLVLSI
2009
IEEE
123views VLSI» more  GLVLSI 2009»
15 years 6 months ago
Power efficient tree-based crosslinks for skew reduction
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G...
VLSID
2005
IEEE
87views VLSI» more  VLSID 2005»
16 years 2 days ago
Synthesis of Asynchronous Circuits Using Early Data Validity
Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable stat...
Nitin Gupta, Doug A. Edwards
ASPDAC
2000
ACM
95views Hardware» more  ASPDAC 2000»
15 years 4 months ago
FSM decomposition by direct circuit manipulation applied to low power design
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
José C. Monteiro, Arlindo L. Oliveira
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
15 years 8 months ago
Vdd programmability to reduce FPGA interconnect power
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
Fei Li, Yan Lin, Lei He