433 search results - page 13 / 87 » Activity-driven clock design for low power circuits |
GLVLSI
2006
IEEE
15 years 5 months ago
2006
IEEE
Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
118
click to vote
DSD
2006
IEEE
15 years 5 months ago
2006
IEEE
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption h...
ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...
ASPDAC
2005
ACM
15 years 5 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
ASPDAC
1999
ACM
15 years 4 months ago
1999
ACM
– In this paper, we introduce a high-speed and low power Phase-Frequency Detector (PFD) that is designed using modified TSPC (True Single-Phase Clock) positive edge triggered D f...