433 search results - page 15 / 87 » Activity-driven clock design for low power circuits |
DAC
1999
ACM
15 years 4 months ago
1999
ACM
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
DAC
2001
ACM
16 years 21 days ago
2001
ACM
This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ...
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ISLPED
2009
ACM
15 years 6 months ago
2009
ACM
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
PATMOS
2005
Springer
15 years 5 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
ISCAS
2002
IEEE
15 years 4 months ago
2002
IEEE