433 search results - page 17 / 87 » Activity-driven clock design for low power circuits |
103
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ASPDAC
2008
ACM
15 years 1 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
106
Voted
DAC
2000
ACM
16 years 21 days ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
105
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TVLSI
2010
14 years 6 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...