433 search results - page 18 / 87 » Activity-driven clock design for low power circuits |
FPL
2007
Springer
15 years 5 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
102
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DAC
2005
ACM
15 years 1 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
SAMOS
2007
Springer
15 years 5 months ago
2007
Springer
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
66
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ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
A low-power output feedback controlled frequency synthesizer. Our proposed circuit can be used for low-power multiplier is proposed for Delay Locked Loop (DLL) based application an...