433 search results - page 19 / 87 » Activity-driven clock design for low power circuits |
120
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ISLPED
1998
ACM
15 years 4 months ago
1998
ACM
Multi-Voltage CMOS MVCMOS is a design methodology for very low power supply voltages that uses low-threshold transistors in series with the supply rails. The control voltages on...
ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
DAC
2008
ACM
16 years 22 days ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
100
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GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
DATE
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...