433 search results - page 22 / 87 » Activity-driven clock design for low power circuits |
GLVLSI
2010
IEEE
15 years 4 months ago
2010
IEEE
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
VLSID
2005
IEEE
16 years 4 days ago
2005
IEEE
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
89
Voted
ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
The power consumption of a sequential circuit can be reduced by decomposing it into subcircuits which can be turned off when inactive. Power can also be reduced by careful state e...
114
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ISPD
2004
ACM
15 years 5 months ago
2004
ACM
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
113
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DAC
2008
ACM
15 years 1 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...