433 search results - page 24 / 87 » Activity-driven clock design for low power circuits |
APCCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
ISLPED
2005
ACM
15 years 5 months ago
2005
ACM
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
105
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ASPDAC
2009
ACM
15 years 6 months ago
2009
ACM
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
105
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IJON
2007
14 years 11 months ago
2007
— This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...