433 search results - page 29 / 87 » Activity-driven clock design for low power circuits |
114
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DAC
2008
ACM
16 years 2 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
106
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ICCD
2005
IEEE
15 years 11 months ago
2005
IEEE
: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce...
120
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IOLTS
2005
IEEE
15 years 7 months ago
2005
IEEE
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
130
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DAC
2003
ACM
16 years 2 months ago
2003
ACM
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
107
Voted
ISLPED
2004
ACM
15 years 7 months ago
2004
ACM
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...