433 search results - page 30 / 87 » Activity-driven clock design for low power circuits |
120
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CORR
2010
Springer
14 years 9 months ago
2010
Springer
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
DAC
2009
ACM
16 years 2 months ago
2009
ACM
Power and performance benefits of scaling are lost to worst case margins as uncertainty of device characteristics is increasing. Adaptive techniques can dynamically adjust the mar...
105
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ICCD
2004
IEEE
15 years 11 months ago
2004
IEEE
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
VLSID
2004
IEEE
16 years 2 months ago
2004
IEEE
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
149
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SENSYS
2009
ACM
15 years 8 months ago
2009
ACM
Clock synchronization is highly desirable in many sensor networking applications. It enables event ordering, coordinated actuation, energy-efficient communication and duty cyclin...