433 search results - page 43 / 87 » Activity-driven clock design for low power circuits |
115
click to vote
DAC
2005
ACM
15 years 3 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
101
click to vote
CCECE
2009
IEEE
15 years 6 months ago
2009
IEEE
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6ȝm CMOS. The implemented CDR comprises a phase-an...
DATE
2010
IEEE
15 years 7 months ago
2010
IEEE
—In this paper we study the effectiveness of two power gating methods – transistor switches and MEMS switches – in reducing the power consumption of a design with a certain t...
DAC
2009
ACM
15 years 8 months ago
2009
ACM
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
ACSD
2010
IEEE
15 years 11 hour ago
2010
IEEE
Abstract--Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step pr...