433 search results - page 45 / 87 » Activity-driven clock design for low power circuits |
108
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ASPDAC
2008
ACM
15 years 4 months ago
2008
ACM
This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage ...
117
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ASYNC
2005
IEEE
15 years 7 months ago
2005
IEEE
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
114
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DATE
1999
IEEE
15 years 6 months ago
1999
IEEE
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
106
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ISLPED
1995
ACM
15 years 5 months ago
1995
ACM
A dual-rail CMOS adiabatic switching circuit approach is described which follows the electroid model of Hall. These circuits can operate in either the retractile cascade or the re...
118
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DAC
2001
ACM
16 years 2 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...