433 search results - page 47 / 87 » Activity-driven clock design for low power circuits |
118
click to vote
JUCS
2007
15 years 1 months ago
2007
: The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this artic...
107
click to vote
ISCAS
1995
IEEE
15 years 5 months ago
1995
IEEE
— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley S...
110
click to vote
ICCAD
1994
IEEE
15 years 6 months ago
1994
IEEE
This work presents techniques for computing the switching activities of all circuit nodes under pseudorandom or biased input sequences and assuming a zero delay mode of operation....
115
click to vote
ISQED
2002
IEEE
15 years 6 months ago
2002
IEEE
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consu...
114
click to vote
ICCD
2001
IEEE
15 years 11 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...