433 search results - page 48 / 87 » Activity-driven clock design for low power circuits |
119
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ISVLSI
2005
IEEE
15 years 7 months ago
2005
IEEE
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
120
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DAC
1997
ACM
15 years 6 months ago
1997
ACM
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
103
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ICCD
2005
IEEE
15 years 11 months ago
2005
IEEE
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
136
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GLVLSI
2010
IEEE
15 years 6 months ago
2010
IEEE
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
103
Voted
DATE
2009
IEEE
15 years 8 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...