433 search results - page 4 / 87 » Activity-driven clock design for low power circuits |
DAC
2003
ACM
15 years 10 months ago
2003
ACM
In this work, we report on an unprecedented design where digital, analog, and MEMS technologies are combined to realize a generalpurpose single-chip CMOS microsystem. The converge...
ISLPED
1999
ACM
15 years 1 months ago
1999
ACM
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
TVLSI
2008
14 years 9 months ago
2008
Recently we proposed a new clocking scheme, injection-locked clocking (ILC), to combat deteriorating clock skew and jitter, and hence reduce power consumption in highperformance mi...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...