433 search results - page 51 / 87 » Activity-driven clock design for low power circuits |
131
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QEST
2010
IEEE
14 years 12 months ago
2010
IEEE
Traditional architecture design approaches hide hardware uncertainties from the software stack through overdesign, which is often expensive in terms of power consumption. The recen...
106
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ISCAS
2007
IEEE
15 years 8 months ago
2007
IEEE
- In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has be...
ISVLSI
2008
IEEE
15 years 8 months ago
2008
IEEE
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
ASPDAC
1998
ACM
15 years 6 months ago
1998
ACM
-- The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET fl...
113
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PATMOS
2004
Springer
15 years 7 months ago
2004
Springer
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...