Sciweavers

433 search results - page 52 / 87
» Activity-driven clock design for low power circuits
Sort
View
CACM
2000
158views more  CACM 2000»
15 years 1 months ago
Wireless Integrated Network Sensors
Wireless Integrated Network Sensors (WINS) now provide a new monitoring and control capability for transportation, manufacturing, health care, environmental monitoring, and safety...
Gregory J. Pottie, William J. Kaiser
65
Voted
VLSID
2004
IEEE
85views VLSI» more  VLSID 2004»
16 years 2 months ago
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System
A key component of the Data-Intensive Architecture (DIVA) is the Processing-In-Memory (PIM) Routing Component (PiRC) that is responsible for efficient communication between PIM ch...
Sumit D. Mediratta, Jeff Sondeen, Jeffrey T. Drape...
80
Voted
ISLPED
1996
ACM
83views Hardware» more  ISLPED 1996»
15 years 6 months ago
12-b 125 MSPS CMOS D/A designed for spectral performance
A 12-b 125 MSPS, digital to analog converter fabricated on a 0.6 micron single poly double metal CMOS process is presented. The design operates on supply voltages from 2.7 to 5.5 ...
Douglas Mercer, Larry Singer
TVLSI
2002
366views more  TVLSI 2002»
15 years 1 months ago
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wa...
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
15 years 8 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami