433 search results - page 54 / 87 » Activity-driven clock design for low power circuits |
120
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DAC
1994
ACM
15 years 6 months ago
1994
ACM
Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an ecient modular partitioning approach for asynchronous c...
130
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ISQED
2006
IEEE
15 years 8 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
109
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ASYNC
2000
IEEE
15 years 6 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
122
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DATE
2007
IEEE
15 years 8 months ago
2007
IEEE
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as hig...
105
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ISCAS
2008
IEEE
15 years 8 months ago
2008
IEEE
—We present experimental results from an integrated circuit designed for wireless neural recording applications. The chip, which was fabricated in a 0.6-µm 2P3M BiCMOS process, ...