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» Activity-driven clock design for low power circuits
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ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
15 years 5 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
15 years 7 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
ISPD
2005
ACM
126views Hardware» more  ISPD 2005»
15 years 7 months ago
Effects of on-chip inductance on power distribution grid
With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We pe...
Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi O...
CODES
2008
IEEE
15 years 8 months ago
System-level mitigation of WID leakage power variability using body-bias islands
Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ...
Siddharth Garg, Diana Marculescu
GLVLSI
2009
IEEE
167views VLSI» more  GLVLSI 2009»
15 years 8 months ago
Dual-threshold pass-transistor logic design
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...