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» Activity-driven clock design for low power circuits
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HPCA
2005
IEEE
15 years 7 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ICRA
2009
IEEE
147views Robotics» more  ICRA 2009»
15 years 8 months ago
Milligram-scale high-voltage power electronics for piezoelectric microrobots
— Piezoelectric actuators can achieve high efficiency and power density in very small geometries, which shows promise for microrobotic applications, such as flapping-wing robot...
Michael Karpelson, Gu-Yeon Wei, Robert J. Wood
PATMOS
2005
Springer
15 years 7 months ago
Enhanced GALS Techniques for Datapath Applications
Abstract. Based on a previously reported request driven technique for Globally-Asynchronous Locally-Synchronous (GALS) circuits this paper presents two significant enhancements. Fi...
Eckhard Grass, Frank Winkler, Milos Krstic, Alexan...
ISLPED
2003
ACM
113views Hardware» more  ISLPED 2003»
15 years 7 months ago
Reducing power density through activity migration
Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Exc...
Seongmoo Heo, Kenneth C. Barr, Krste Asanovic
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
15 years 6 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha