433 search results - page 5 / 87 » Activity-driven clock design for low power circuits |
CDES
2006
14 years 11 months ago
2006
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
VLSID
2006
IEEE
15 years 10 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
ASPDAC
2000
ACM
15 years 1 months ago
2000
ACM
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...
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Voted
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...