433 search results - page 60 / 87 » Activity-driven clock design for low power circuits |
104
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ISVLSI
2006
IEEE
15 years 8 months ago
2006
IEEE
We describe a new latch circuit designed to give a high performance in low voltage synchronizer applications. By increasing the latch current only during metastability, we can mor...
125
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TDSC
2010
15 years 8 days ago
2010
—Soft errors (or Transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft ...
102
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DAC
2007
ACM
16 years 2 months ago
2007
ACM
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...
VLSID
2005
IEEE
16 years 2 months ago
2005
IEEE
Two Simple structures of low-power Dual-edge triggered Static Pulsed Flip-Flops (DSPFF) are presented in this paper. They are composed of a dualedge pulse generator and a static f...
127
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MJ
2007
15 years 1 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...