433 search results - page 61 / 87 » Activity-driven clock design for low power circuits |
124
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DAC
2005
ACM
15 years 3 months ago
2005
ACM
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
124
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NOCS
2010
IEEE
14 years 11 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
118
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DAC
2009
ACM
15 years 5 months ago
2009
ACM
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...
125
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VLSID
2006
IEEE
15 years 8 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
111
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ISCAS
2007
IEEE
15 years 8 months ago
2007
IEEE
Abstract— This paper reports the design of a high performance, adaptive low/high swing CMOS driver circuit (mj–driver) suitable for driving of global interconnects with large c...