433 search results - page 62 / 87 » Activity-driven clock design for low power circuits |
108
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ASPDAC
2010
ACM
14 years 12 months ago
2010
ACM
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
114
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GLVLSI
2008
IEEE
15 years 8 months ago
2008
IEEE
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
120
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ISCAS
2003
IEEE
15 years 7 months ago
2003
IEEE
Abstract— The design of robust and area efficient power distribution networks for high speed, high complexity integrated circuits has become a challenging task. The integrity of...
117
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ISQED
2009
IEEE
15 years 8 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
130
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DFT
2004
IEEE
15 years 5 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...