433 search results - page 67 / 87 » Activity-driven clock design for low power circuits |
148
Voted
NOCS
2008
IEEE
15 years 8 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
115
Voted
ARITH
2009
IEEE
15 years 8 months ago
2009
IEEE
Moduli of the form 2n ± 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs fo...
77
Voted
ASPDAC
1999
ACM
15 years 6 months ago
1999
ACM
- We describe an integrated model of the hardware and the battery sub-systems in batterypowered VLSI systems. We demonstrate that, under this model and for a fixed operating voltag...
87
Voted
ITC
1998
IEEE
15 years 6 months ago
1998
IEEE
A method for measuring inter-symbol interference, duty cycle distortion, random jitter and periodic jitter is described. The Blackman-Tukey method of signal analysis is used. This...
74
Voted
ENGL
2007
15 years 1 months ago
2007
—In this paper we propose a gain-variable low noise amplifier (LNA) for low-voltage and low power WCDMA application. The LNA is designed based on a current-reused topology and a ...