433 search results - page 68 / 87 » Activity-driven clock design for low power circuits |
119
Voted
ISLPED
1997
ACM
15 years 5 months ago
1997
ACM
Significand pre-alignment is a pre requisite for floating point additions. This paper1 addresses the architectural design and energy delay evaluation of a Low Power Barrel Switch ...
106
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DAC
2004
ACM
16 years 2 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
117
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IJCSA
2008
15 years 1 months ago
2008
This paper presents a comparison relating two different vision system architectures. The first one involves a smart sensor including analog processors allowing on-chip image proce...
146
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CASES
2008
ACM
15 years 3 months ago
2008
ACM
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
136
Voted
DAC
2008
ACM
15 years 3 months ago
2008
ACM
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-...