433 search results - page 6 / 87 » Activity-driven clock design for low power circuits |
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
ISLPED
1998
ACM
15 years 1 months ago
1998
ACM
Adiabatic logic promises extremely low power consumption for those applications where slower clock rates are acceptable. However, there have been very few adiabatic memory designs...
ISLPED
2010
ACM
14 years 9 months ago
2010
ACM
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
ISLPED
2007
ACM
14 years 11 months ago
2007
ACM
Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabl...