433 search results - page 70 / 87 » Activity-driven clock design for low power circuits |
124
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ASYNC
2006
IEEE
15 years 8 months ago
2006
IEEE
Distributed sensor networks, human body implants, and hand-held electronics have tight energy budgets that necessitate low power circuits. Most of these devices include an analog-...
129
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FPL
2006
Springer
15 years 5 months ago
2006
Springer
Given large circuit sizes, high clock frequencies, and possibly extreme operating environments, Field Programmable Gate Arrays (FPGAs) are capable of heating beyond their designed...
114
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DAC
2008
ACM
16 years 2 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
107
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ISCA
2008
IEEE
15 years 8 months ago
2008
IEEE
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-t...
124
Voted
ICCAD
2007
IEEE
15 years 3 months ago
2007
IEEE
– Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and ...