433 search results - page 72 / 87 » Activity-driven clock design for low power circuits |
107
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ATS
2005
IEEE
15 years 3 months ago
2005
IEEE
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...
GLVLSI
2003
IEEE
15 years 7 months ago
2003
IEEE
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
117
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GLVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
FTEDA
2008
15 years 1 months ago
2008
With greater integration, the power dissipation in integrated circuits has begun to outpace the ability of today's heat sinks to limit the on-chip temperature. As a result, t...
130
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VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...