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» Activity-driven clock design for low power circuits
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CASES
2007
ACM
15 years 5 months ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
110
Voted
ISLPED
1997
ACM
116views Hardware» more  ISLPED 1997»
15 years 6 months ago
Power reduction techniques for a spread spectrum based correlator
This paper presents the design of a low power spread spectrum correlator. We look at two major approaches and evaluate the best alternative for power reduction. We first consider...
David Garrett, Mircea R. Stan
IPSN
2005
Springer
15 years 7 months ago
Perpetual environmentally powered sensor networks
— Environmental energy is an attractive power source for low power wireless sensor networks. We present Prometheus, a system that intelligently manages energy transfer for perpet...
Xiaofan Jiang, Joseph Polastre, David E. Culler
ISQED
2009
IEEE
86views Hardware» more  ISQED 2009»
15 years 8 months ago
Uncriticality-directed scheduling for tackling variation and power challenges
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability...
Toshinori Sato, Shingo Watanabe
DAC
1999
ACM
16 years 2 months ago
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...
Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton,...