433 search results - page 81 / 87 » Activity-driven clock design for low power circuits |
91
Voted
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
CODES
2008
IEEE
15 years 4 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
86
Voted
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amoun...
ISLPED
2010
ACM
14 years 9 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
255
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Publication
Global Positioning System (GPS) Technology allows precise determination of location, velocity, direction, and time. The price of GPS receivers is falling rapidly and the applicatio...