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» Activity-driven clock design for low power circuits
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77
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GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
15 years 2 months ago
A low power direct digital frequency synthesizer with 60 dBc spectral purity
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
J. M. Pierre Langlois, Dhamin Al-Khalili
62
Voted
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
15 years 10 months ago
Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing
Abstract--A novel input and output biasing circuit to extend the input common mode (CM) voltage range and the output swing to rail-to-rail in a low voltage op-amp in standard CMOS ...
S. V. Gopalaiah, A. P. Shivaprasad, Sukanta K. Pan...
DAC
2005
ACM
14 years 11 months ago
Keeping hot chips cool
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
DAC
2005
ACM
15 years 10 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo
IEICET
2008
78views more  IEICET 2008»
14 years 9 months ago
Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
Takashi Takeuchi, Yu Otake, Masumi Ichien, Akihiro...