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ISLPED
1995
ACM
116views Hardware» more  ISLPED 1995»
15 years 1 months ago
Activity-sensitive architectural power analysis for the control path
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing ...
Paul E. Landman, Jan M. Rabaey
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
15 years 2 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
15 years 9 months ago
Register Transfer Operation Analysis during Data Path Verification
A control part ? data path partition based sequential circuit verification scheme aimed at avoiding state explosion comprises two major modules namely, a data path verifier and a ...
D. Sarkar
DAC
1997
ACM
15 years 1 months ago
Power Management Techniques for Control-Flow Intensive Designs
This paper presents a low-overhead controller-based power managementtechnique that re-specifies control signals to reconfigure existing multiplexer networks and functional units t...
Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazuto...
DAC
2006
ACM
15 years 10 months ago
Efficient detection and exploitation of infeasible paths for software timing analysis
Accurate estimation of the worst-case execution time (WCET) of a program is important for real-time embedded software. Static WCET estimation involves program path analysis and ar...
Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, T...