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» Adapting cache line size to application behavior
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92
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ICS
1999
Tsinghua U.
15 years 3 months ago
Adapting cache line size to application behavior
A cache line size has a signi cant e ect on missrate and memorytra c. Today's computers use a xed line size, typically 32B, which may not be optimalfor a given application. O...
Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gup...
86
Voted
IMS
2000
125views Hardware» more  IMS 2000»
15 years 2 months ago
Compiler-Directed Cache Line Size Adaptivity
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbau...
109
Voted
PARCO
2003
15 years 6 days ago
Cache Memory Behavior of Advanced PDE Solvers
Three different partial differential equation (PDE) solver kernels are analyzed in respect to cache memory performance on a simulated shared memory computer. The kernels implement...
Dan Wallin, Henrik Johansson, Sverker Holmgren
HPCA
2006
IEEE
15 years 11 months ago
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
Aamer Jaleel, Matthew Mattina, Bruce L. Jacob
96
Voted
CASES
2006
ACM
15 years 4 months ago
Adaptive object code compression
Previous object code compression schemes have employed static and semiadaptive compression algorithms to reduce the size of instruction memory in embedded systems. The suggestion ...
John Gilbert, David M. Abrahamson