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» Adapting cache line size to application behavior
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ICDCS
1996
IEEE
13 years 10 months ago
The Performance Value of Shared Network Caches in Clustered Multiprocessor Workstations
This paper evaluates the bene t of adding a shared cache to the network interface as a means of improving the performance of networked workstations con gured as a distributed shar...
John K. Bennett, Katherine E. Fletcher, William Ev...
ICPP
2009
IEEE
13 years 4 months ago
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...
HIPEAC
2009
Springer
13 years 11 months ago
Revisiting Cache Block Superloading
Abstract. Technological advances and increasingly complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application charac...
Matthew A. Watkins, Sally A. McKee, Lambert Schael...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
13 years 11 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
ICS
1995
Tsinghua U.
13 years 9 months ago
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
Antonio González, Carlos Aliagas, Mateo Val...