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ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
14 years 11 months ago
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
101
Voted
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
16 years 8 hour ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
TCAD
2010
124views more  TCAD 2010»
14 years 6 months ago
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
111
Voted
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
15 years 8 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
COMCOM
2004
118views more  COMCOM 2004»
14 years 11 months ago
The next frontier for communications networks: power management
Storage, memory, processor, and communications bandwidth are all relatively plentiful and inexpensive. However, a growing expense in the operation of computer networks is electric...
Kenneth J. Christensen, Chamara Gunaratne, Bruce N...