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ICCD
2003
IEEE
89views Hardware» more  ICCD 2003»
15 years 11 months ago
Power-Time Tradeoff in Test Scheduling for SoCs
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
Mehrdad Nourani, James Chin
DATE
2010
IEEE
120views Hardware» more  DATE 2010»
15 years 11 months ago
Memory testing with a RISC microcontroller
—Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not ...
A. J. van de Goor, Georgi Gaydadjiev, Said Hamdiou...
DATE
2000
IEEE
113views Hardware» more  DATE 2000»
15 years 10 months ago
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
15 years 10 months ago
Deterministic Test Pattern Generation Techniques for Sequential Circuits
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
Ilker Hamzaoglu, Janak H. Patel
ITC
2000
IEEE
76views Hardware» more  ITC 2000»
15 years 10 months ago
System issues in boundary-scan board test
Boards have evolved into complex systems and even collections of interacting systems. Test engineers struggle to find out how these systems are initialized and booted because of p...
Kenneth P. Parker