173 search results - page 14 / 35 » Adaptive execution techniques for SMT multiprocessor archite... |
DAC
2006
ACM
16 years 25 days ago
2006
ACM
ing models and HW-SW Interfaces Abstraction for Multi-Processor SoC Ahmed A. Jerraya TIMA Laboratory 46 Ave Felix Viallet 38031 Grenoble CEDEX, France +33476574759 Ahmed.Jerraya@im...
ISCA
2010
IEEE
15 years 4 months ago
2010
IEEE
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
PDPTA
2004
15 years 1 months ago
2004
High-throughput real-time systems require non-standard and costly hardware and software solutions. Modern workstation can represent a credible alternative to develop realtime inte...
ISCA
2006
IEEE
15 years 5 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
IPPS
2000
IEEE
15 years 4 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...