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APSCC
2010
IEEE
14 years 10 months ago
A Multicore-Aware Runtime Architecture for Scalable Service Composition
Middleware for web service orchestration, such as runtime engines for executing business processes, workflows, or web service compositions, can easily become performance bottleneck...
Daniele Bonetta, Achille Peternier, Cesare Pautass...
ISPASS
2007
IEEE
15 years 6 months ago
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
Matt T. Yourst
DAC
2011
ACM
13 years 11 months ago
Customer-aware task allocation and scheduling for multi-mode MPSoCs
Today’s multiprocessor system-on-a-chip (MPSoC) products typically have multiple execution modes, and for each mode, all the products utilize the same task allocation and schedu...
Lin Huang, Rong Ye, Qiang Xu
CBSE
2006
Springer
15 years 3 months ago
A Process for Resolving Performance Trade-Offs in Component-Based Architectures
Designing architectures requires the balancing of multiple system quality objectives. In this paper, we present techniques that support the exploration of the quality properties of...
Egor Bondarev, Michel R. V. Chaudron, Peter H. N. ...
HPCA
2001
IEEE
16 years 7 days ago
Self-Tuned Congestion Control for Multiprocessor Networks
Network performance in tightly-coupled multiprocessors typically degrades rapidly beyond network saturation. Consequently, designers must keep a network below its saturation point...
Mithuna Thottethodi, Alvin R. Lebeck, Shubhendu S....