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IWMM
2010
Springer
118views Hardware» more  IWMM 2010»
15 years 4 months ago
Speculative parallelization using state separation and multiple value prediction
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
Chen Tian, Min Feng, Rajiv Gupta
IPPS
2005
IEEE
15 years 5 months ago
Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
Yun Zhang, Michael Voss
ASPLOS
2009
ACM
16 years 15 days ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
HPCA
2006
IEEE
16 years 6 days ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
ASPDAC
2009
ACM
110views Hardware» more  ASPDAC 2009»
15 years 6 months ago
Variability-aware robust design space exploration of chip multiprocessor architectures
Abstract— In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufactu...
Gianluca Palermo, Cristina Silvano, Vittorio Zacca...