47 search results - page 4 / 10 » Adaptive prefetching for shared cache based chip multiproces... |
MAM
2002
13 years 6 months ago
2002
Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of small- to medium-scale parallel machines t...
SC
1995
ACM
13 years 9 months ago
1995
ACM
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
DSD
2003
IEEE
13 years 11 months ago
2003
IEEE
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
ICPP
2008
IEEE
14 years 21 days ago
2008
IEEE
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
CC
2010
Springer
14 years 1 months ago
2010
Springer
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...