13 search results - page 1 / 3 » Adaptive set pinning: managing shared caches in chip multipr... |
73
Voted
ASPLOS
2008
ACM
15 years 7 days ago
2008
ACM
98
Voted
HIPEAC
2009
Springer
15 years 2 months ago
2009
Springer
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...
66
Voted
DATE
2009
IEEE
15 years 5 months ago
2009
IEEE
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
86
Voted
HPCA
2007
IEEE
15 years 4 months ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
86
Voted
IEEEPACT
2008
IEEE
15 years 4 months ago
2008
IEEE
Chip Multiprocessors (CMPs) allow different applications to concurrently execute on a single chip. When applications with differing demands for memory compete for a shared cache, ...