233 search results - page 17 / 47 » Address Code Generation for Digital Signal Processors |
102
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CASES
2005
ACM
15 years 1 months ago
2005
ACM
Digital Signal Processing (DSP) is becoming increasingly widespread in portable devices. Due to harsh constraints on power, latency, and throughput in embedded environments, devel...
CONCURRENCY
2006
14 years 11 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
ISCAS
2005
IEEE
15 years 5 months ago
2005
IEEE
: This paper presents a self-calibration method for designing high speed pipeline ADCs. Unlike all existing calibration algorithms, the proposed calibration does not insert any tes...
118
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PAMI
2011
14 years 6 months ago
2011
—We show that, via temporal modulation, one can observe and capture a high-speed periodic video well beyond the abilities of a low-frame-rate camera. By strobing the exposure wit...
CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...